EDN

Estimating Power Dissipation in CMOS Devices

This application note describes ways to estimate power dissipation of individual CMOS logic devices in a system. It will help users determine if their designs raise any power dissipation concerns. Due ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
Electronic Design

CMOS DAC Family Combines Low-Power Dissipation With Broadband Capability

The AD9751, AD9753, AD9755 TxDAC+ family of 10-, 12- and 14-bit D/A converters are manufactured using a 0.35-µm CMOS process to reduce chip power dissipation by 40%. In addition, the DACs can ...
Design-Reuse

Low Power Universal Gates for Approximate Computing

Density and speed of IC’s have increased exponentially for several decades, following a trend described by Moore’s Law. While it is accepted that this exponential improvement trend will end, it is ...
Nature

Current-Mode Logic and Low-Power CMOS Technology

Current-Mode Logic (CML) and low-power Complementary Metal-Oxide-Semiconductor (CMOS) technology continue to drive significant advances in digital circuit design, particularly in high-speed and energy ...
EurekAlert!

GaN-based CMOS circuits make power integrated systems more efficient

In recent years, gallium nitride (GaN) has emerged as a compelling candidate to complement the silicon material used in wireless communication and power conversion applications. Benefits of GaN ...
Electronic Design

SiGe BiCMOS Vs. CMOS For Signal Conditioning

Texas Instrument's Richard Zarr reviews the differences between Silicon-Germanium BiCMOS and small-geometry CMOS when it comes to driving high-speed data transmission lines. The CMOS process was the ...