Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Linux Journal

Xilinx FPGA Design Tools for Linux

A field programmable gate array (FPGA) is a user-programmable piece of silicon constructed in very large-scale integration (VLSI) technology. The VLSI transistor-level detail is absolutely predefined ...
EDN

Xilinx Spartan-6 FPGA User Guide Lite

What is the purpose of this paper? This paper gives potential users an easy-to-grasp idea of the device functions of Xilinx Spartan-6 FPGAs. It describes the functionality of these devices in far more ...
Electronic Design

Pair The Right JESD204B Converter With Your FPGA

With more analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) now supporting the latest JESD204B serial interface standard, questions are arising about the best way to ...