As integrated circuits grow in content and complexity, reaching target yield levels becomes challenging. A product engineer's worst nightmares frequently become reality: sample devices are supposed to ...

Balancing yield and test is essential to semiconductor manufacturing, but it’s becoming harder to determine how much weight to give one versus the other as chips become more specialized for different ...

There is no single solution, but there plenty of room for improvement—and lots of investment around better use of data. Equipment and tools vendors are starting to focus on data as a means of ...

Whether you’re using a leading-edge process node to manufacture a very large system-on-chip (SoC), or using an established node for automotive or Internet of Things (IoT) electronics, critical area ...

Cadence Design Systems has introduced Encounter Diagnostics, a yield diagnostics tool that would identify customers’ critical nanometer-IC yield issues and precisely locate root cause defects.

TSMC is working to optimize its 2nm (N2) technology by reducing variability and defect density, as the manufacturer aims to begin mass production of 2nm process chips in the second half of next year.

According to news reports, Samsung and TSMC are expected to enter 5nm process mass production in 2020. The competition in 5nm wafer yield and market share will be very intense. A brand new wafer ...

ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

The big picture: During his tenure as Intel's CEO, Pat Gelsinger sought to correct a critical strategic misstep that allowed TSMC to surpass Intel in process technology. Gelsinger promised that ...