Although we’ve barely begun the PCI Express 5.0 (PCIe Gen 5) generation, the PCI Special Interest Group is already looking ahead. Beginning in 2025, you can expect the PCIe 7.0 specification to be ...

When system architects sit down to design their next platforms, they start by looking at a bunch of roadmaps from suppliers of CPUs, accelerators, memory, flash, network interface cards – and ...

Computing and communications technologies have advanced along with changing markets, bringing these technologies together at the silicon, board and system levels. The compute industry has evolved ...

Moore’s Law might be slowing down CPU compute capacity increases in recent years, but the innovation has been coming at a steady drumbeat for the interconnects used inside servers and between nodes in ...

Tyco Electronics has designed a 1mm centreline Card Edge Connector to meet the point-to-point, full duplex, I/O Bus standard for PCI Express architecture. The PCI Express standard was introduced to ...

The company's 1-mm centerline card-edge connector meets the high performance point-to-point, full-duplex I/O standard for the PCI Express architecture. Target applications for the connector include ...

NurLogic’s PCI Express PHY IP Design Will Utilize NurLogic’s Silicon-Proven 0.13-micron SerDes PHY Core SAN DIEGO –February 19, 2003 – NurLogic Design, Inc. a developer of high bandwidth ...

There are two significant issues with today’s I/O interconnects: high speed storage and networking applications need more bandwidth than currently available ...

To obtain the highest levels of performance possible with a local-bus interface while using currently available technology, you should treat the layouts and designs for PCI motherboards and add-in ...

Page 2: Radeon X600 and X300 - New PCI Express Solutions From ATi Recently ATi spent time with us going over their soon to be launched PCI Express based offering of 3D Graphics cards. Although we're ...