TriCN,based in San Francisco, claims it has the most area-efficient single lane (x1) PCI Express PHY. Currently available in the TSMC 130nm process, TriCN's PCI Express PHY x1 is the first to achieve ...

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...

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TriCN, announced that it has established an industry precedent with the most area-efficient single lane (x1) PCI Express PHY. Currently available in the TSMC 130nm process, TriCN's PCI Express PHY x1 ...

Delivers data rate of up to 64 GT/s for high-performance workloads Supports the full feature set of PCIe 6.0 with PHY support for CXL 3.0 Offers complete IP solution optimized for latency, power, and ...

HSINCHU, Taiwan--(BUSINESS WIRE)--United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, and Faraday Technology Corporation (TWSE: 3035), a ...

The PCIe specification has given a specific Link Training and Status State Machine (LTSSM) state named Loopback, which is intended for test and fault isolation use. Basically, it gives a mechanism ...

Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced that it will demonstrate PCIe® 8.0 SerDes running at 256 gigatransfers-per-second ...

In late February 2026, Marvell Technology showcased PCIe 8.0 SerDes running at 256 gigatransfers-per-second at DesignCon 2026 in Santa Clara, highlighting advances aimed at supporting AI and data ...