Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel ...

Rapidus plans to outline its early-stage work on panel-level packaging using 600 × 600 mm glass substrates at SEMICON Japan, ...

An insatiable demand for logic to memory integration for AI and high-performance computing is driving progress toward very large-format packages, which are expected to approach 10 times the maximum ...

Panel maker Innolux is looking to venture into the IC packaging segment by converting its 3.5G LCD panel fab into an advanced packaging plant dedicated to FOPLP (fan-out panel level package) process, ...

The Firefly G3 system delivers unique inspection and metrology process control technologies aimed at buried defects and voids supporting next generations of glass and copper clad laminate (CCL) The ...

TSMC is exploring a 'radically new' method of semiconductor chip packaging, as the world of AI is simply not slowing down and needs further advancements at every level to keep up. TSMC Is reportedly ...

Thanks to the AI tsunami, demand for AI chips from all sectors is continuing to surge. The Chip-on-Wafer-on-Substrate (CoWoS) architecture that dominates existing 2.5D and 3D packaging technologies is ...